1. Field of the Invention
The present invention relates to semiconductor packages, and more particularly, to a semiconductor package having an interposer and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are becoming lighter, thinner, shorter and smaller. To meet the demands for high integration and miniaturization of electronic products, various types of packages such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages have been developed by using flip-chip technologies so as to increase circuit densities, reduce chip packaging sizes and shorten signal transmission paths.
However, in a flip-chip packaging process, conductive bumps of a semiconductor chip crack easily under thermal stresses caused by a big CTE (Coefficient of Thermal Expansion) mismatch between the semiconductor chip and the corresponding packaging substrate, thereby adversely affecting the formation of joints between the conductive bumps of the semiconductor chip and the correspondingly packaging substrate and easily resulting in delamination of solder bumps from the packaging substrate.
Further, along with increased integration of integrated circuits, CTE mismatches between chips and packaging substrates induce more thermal stresses and lead to more serious warpages, thereby reducing the product reliability and resulting in failure of reliability tests.
Conventionally, a plurality of chips are disposed on a packaging substrate in a 2D manner. Accordingly, when the number of the chips increases, the area of the packaging substrate must be increased, which, however, does not meet the demands for miniaturization and high performance of electronic products.
Further, as the circuit density of semiconductor chips continuously increases, the pitch between electrode pads of the semiconductor chips reaches the nanometer scale. On the other hand, the pitch between contacts of packaging substrates are only at the micrometer scale and cannot effectively match the pitch between the electrode pads of the semiconductor chips, thus adversely affecting the fabrication of electronic products.
To overcome the above-described drawbacks, an interposer made of a semiconductor material is provided and a 3D stacking technique is used for connecting a semiconductor chip to a packaging substrate.
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1. Referring to FIG. 1, a silicon interposer 11 is sandwiched between a packaging substrate 10 and a semiconductor chip 14. To form the silicon interposer 11, a plurality of through silicon vias (TSVs) 110 are formed to penetrate a silicon wafer, an RDL (redistribution layer) structure 111 is formed through a semiconductor process on one side of the silicon wafer and a plurality of conductive bumps 12a are formed on the other side of the silicon wafer. Then, the silicon wafer is cut into a plurality of silicon interposers 11. Each of the silicon interposers 11 is disposed on an upper side of a packaging substrate 10 via the conductive bumps 12a and an underfill 12b is filled between the silicon interposer 11 and the packaging substrate 10 for encapsulating the conductive bumps 12a. Thereafter, at least a semiconductor chip 14 is disposed on the silicon interposer 11 and electrically connected to the RDL structure 111 through a plurality of conductive bumps 14a. The RDL structure 111 allows the silicon interposer 11 to receive more than one semiconductor chip 14 without the need to increase the area of the silicon interposer 11. Then, an underfill 14b is filled between the silicon interposer 11 and the semiconductor chip 14 for encapsulating the conductive bumps 14a. Thereafter, a plurality of solder balls 15 are formed on a lower side of the packaging substrate 10 for connecting the semiconductor package to a circuit board.
Through the silicon interposer 11, the semiconductor chip 14 having a high circuit density is connected to the packaging substrate 10.
Since the silicon interposer 11 has a CTE equal or close to that of the semiconductor chip 14, cracking of the conductive bumps 14a between the semiconductor chip 14 and the silicon interposer 11 is prevented, thereby effectively improving the product reliability.
Compared with a conventional flip-chip package, the semiconductor package 1 has reduced length and width. For example, the packaging substrate of the conventional flip-chip package has a minimum line width of 12 um and a minimum line pitch of 12 um. When the number of the electrode pads of the semiconductor chip of the conventional flip-chip package increases, since the line width/line pitch of the packaging substrate can not be reduced, the area of the packaging substrate must be increased to accommodate more circuits for electrically connecting the semiconductor chip and the packaging substrate. On the other hand, through a semiconductor process, the silicon interposer 11 of the semiconductor package 1 has a line width below 3 um and a line pitch blow 3 um. Therefore, the silicon interposer 2 can be electrically connected to the semiconductor chip 14 having a high I/O number without the need to increase the area of the packaging substrate 10. As such, the semiconductor chip 14 is electrically connected to the packaging substrate 10 through the silicon interposer 11.
In addition, the fine-line/fine-pitch characteristic of the silicon interposer 2 leads to short electrical transmission distance and high electrical transmission speed of the semiconductor chip 14.
However, conventionally, both the semiconductor chip 14 and the silicon interposer 11 are thinned before the semiconductor chip 14 is disposed on and electrically connected to the silicon interposer 11. Therefore, warpage easily occurs to the silicon interposer 11 and consequently it is difficult to dispose and electrically connect the semiconductor chip 14 to the silicon interposer 11. To overcome the drawbacks, the silicon interposer 11 is required to have a certain thickness, which, however, hinders the miniaturization of the semiconductor package 1.
Further, although a plurality of semiconductor chips 14 can be disposed on the silicon interposer 11 in a 2D manner to improve the product functionality, it cannot meet the multi-function requirement of electronic products.
Furthermore, to dispose a plurality of semiconductor chips 14 on the silicon interposer 11, the semiconductor chips 14 are conventionally ground first and then disposed on the silicon interposer 11 one by one, thereby greatly increasing the fabrication time and cost. In addition, the semiconductor chips 14 may be thinned to different degrees and hence cannot provide an even surface for stacking and disposing of other chips.
Therefore, how to overcome the above-described drawbacks has become urgent.